1. Field of the Invention
The present invention relates in general to control of video head tracking by detecting auto tracking find (ATF) error in a video cassette tape recorder (VCR), and more particularly to a method and a circuit for detecting an auto tracking find error in a VCR and controlling the capstan phase for correct video head tracking, wherein a phase control range for a capstan is widened so that, when a phase of the capstan is widely deviated, the convergence speed for stabilization of the phase of the capstan can be made fast.
2. Description of the Prior Art
Referring to FIG. 1, there is shown a block diagram of a conventional apparatus for controlling the rotation of a capstan motor in an 8 mm VCR. As shown in this figure, a speed error signal SE is generated based on a difference between a detected rotation speed of the capstan motor 8 and a target rotation speed. An auto tracking find (ATF) signal is detected from a radio frequency (RF) signal of a video signal reproduced from a tape. An auto tracking find (ATF) error is detected based on the ATF signal and a phase error signal PE is generated based on the detected ATF error. The operation of the capstan motor 8 is controlled according to the phase error signal PE and the speed error signal SE. As a result, the auto tracking find operation can be performed.
To put it concretely, the conventional apparatus for controlling the rotation of the capstan motor 8 comprises a rotation speed detector 9 for detecting a rotation speed signal FG corresponding to the rotation speed of the capstan motor 8. The detected rotation speed signal FG from the rotation speed detector 9 is applied to a speed error detecting circuit 1 via a wave shaping circuit 11. In the speed error detecting circuit 1, an interval between adjacent rising edges or between the rising edge and the following falling edge of the rotation speed signal FG is detected and a difference between the detected interval and a target interval of the target rotation speed is also detected. The speed error signal SE is generated in the speed error detecting circuit 1 based on the detected difference.
Upon receiving the video RF signal from the tape, an ATF signal detecting circuit 10 detects the ATF signal from the received video RF signal in response to ATF signal frequency select signals SEL1 and SEL2 and applies the detected ATF signal to an ATF error detecting circuit 3 which generates the ATF signal frequency select signals SEL1 and SEL2 in response to a head switching signal HSW. Also, the ATF error detecting circuit 3 detects the ATF error based on the ATF signal from the ATF signal detecting circuit 10 and generates the phase error signal PE based on the detected ATF error. The speed error signal SE and the phase error signal PE generated in this manner are applied via speed and phase filters 2 and 4 to an adder 5 which adds the applied signals SE and PE. An output signal from the adder 5 is converted into an analog signal in a digital/analog (D/A) converter 6 which applies the analog signal to a motor driving circuit 7 as a drive signal for controlling the rotation of the capstan motor 8. As a result, the rotation speed and phase of the capstan motor 8 can be controlled by the motor driving circuit 7.
On the other hand, as shown in FIG. 2 which is a view illustrating a general detection of the ATF signal in the VCR, recorded on a video tape 21 are pilot signal tracks of frequencies f1-f4 which are disposed inclinedly at a desired angle with respect to a travelling direction of the video tape 21 together with data recorded on the tracks on the video tape 21 in the order of their disposition. For reproduction of the recorded data, the recorded data are reproduced as a video head 22 scans along the tracks on the video tape 21. At this time, in the case where a center position of the video head 22 is scanning the track recorded with the pilot signal of frequency f2, the video head 22 scans also with portions of the adjacent tracks recorded with the pilot signals of the frequencies f1 and f3 respectively as well as the track recorded with the pilot signal of the frequency f2. For this reason, the reproduced RF signal contains the data signal recorded on the center track recorded with the pilot signal of the frequency f2 together with the data signal components recorded on the adjacent tracks having pilot signals of the frequencies f1 and f3 respectively.
Accordingly, assuming that the frequency f2 is selected as an ATF signal frequency based on the ATF signal frequency select signals SEL1 and SEL2 in the ATF signal detecting circuit 10, the ATF signal detecting circuit 10 detects a difference signal between a signal of f1-f2=f.sub.H (about 15.9 KHz) and a signal of f3-f2=3f.sub.H (about 47.1 KHz) among the reproduced pilot frequency signals of f1+f2, f1-f2, f2+f2, f3+f2, f3-f2. The detected difference signal is outputted as the ATF signal through an amplifier having a reference voltage Vcc/2.
Referring to FIG. 3, there is shown a block diagram of the ATF error detecting circuit 3 in the conventional apparatus for controlling the rotation of the capstan motor 8. As shown in this figure, the ATF error detecting circuit 3 comprises an edge detector 3-1 for detecting an edge of the head switching signal HSW, an up-counter 3-2 for inputting an output signal from the edge detector 3-1 as a reset signal and up-counting a clock signal CK in response to the reset signal, a frequency divider 3-4 for frequency-dividing the head switching signal HSW by 2, an ATF signal frequency select signal generator 3-3 for generating the ATF signal frequency select signals SEL1 and SEL2, respectively, at times that a count value from the up-counter 3-2 is in accord with predetermined values based on an output signal 1/2 HSW from the frequency divider 3-4 and the head switching signal HSW, a first ATF check comparator 3-5 for comparing the count value from the up-counter 3-2 with a first ATF check reference value and outputting a control signal E1 at a timing of the ATF signal frequency as a result of the comparison, a second ATF check comparator 3-6 for comparing the count value from the up-counter 3-2 with a second ATF check reference value and outputting a control signal E2 at a timing having a capstan phase difference of .pi. from the tracks recorded with the ATF signal frequency as a result of the comparison, an OR gate 3-7 for ORing the control signals E1 and E2 from the first and second ATF check comparators 3-5 and 3-6, and an analog/digital (A/D) converter 3-8 for converting the analog ATF signal from the ATF signal detecting circuit 10 into digital data in response to an output signal from the OR gate 3-7 as an enable signal. The ATF error detecting circuit 3 also comprises a subtracter 3-9 for subtracting a reference value Dref from the output data from the A/D converter 3-8, a first delay 3-10 for delaying the control signal E1 from the first ATF check comparator 3-5 by the A/D conversion time of the A/D converter 3-8, a second delay 3-11 for delaying the control signal E2 from the second ATF check comparator 3-6 by the A/D conversion time of the A/D converter 3-8, a first latch 3-12 for latching the output data from the subtracter 3-9 in response to an output signal from the first delay 3-10, a second latch 3-13 for latching the output data from the subtracter 3-9 in response to an output signal from the second delay 3-11, a first comparator 3-14 for inputting latch data D.ATF1 from the first latch 3-12 at its non-inverting input terminal and comparing the inputted latch data D.ATF1 with a reference value (ground voltage) input at its inverting input terminal, a second comparator 3-15 for inputting latch data D.ATF2 from the second latch 3-13 at its inverting input terminal and comparing the inputted latch data D.ATF2 with a reference value (ground voltage) input at its non-inverting input terminal, a first switch 3-16 for selecting an upper limit value U.sub.H from an upper limit circuit 3-18 or a lower limit value U.sub.L from a lower limit circuit 3-19 in response to an output signal C.sub.2 from the first comparator 3-14, and a second switch 3-17 for selecting the latch data D.ATF1 from the first latch 3-12 or an output signal from the first switch 3-16 in response to an output signal C.sub.1 from the second comparator 3-15 and outputting the selected signal as the phase error signal PE.
The operation of the ATF error detecting circuit 3 with the above-mentioned construction will hereinafter be described.
Referring to FIGS. 4A to 4G, there are shown timing diagrams of the signals from the respective components in the ATF error detecting circuit 3. First as shown in FIG. 4A, upon input of the head switching signal HSW, the edge of the head switching signal HSW is detected as shown in FIG. 4C in the edge detector 3-1 which applies the detected edge signal as the reset signal to the up-counter 3-2. As shown in FIG. 4D, the up-counter 3-2 up-counts the number of the clocks CK between the edges of the head switching signal HSW in response to the reset signal from the edge detector 3-1. On the other hand, the head switching signal HSW is frequency-divided by 2 as shown in FIG. 4B in the frequency divider 3-4 which applies the 1/2-frequency-divided head switching signal 1/2 HSW to the ATF signal frequency select signal generator 3-3, which outputs the ATF signal frequency select signals SEL1 and SEL2, respectively, at the time that the count value from the up-counter 3-2 is in accord with the predetermined values based on the output signal 1/2 HSW from the frequency divider 3-4 and the head switching signal HSW, as shown in FIG. 4E.
The ATF signal frequency select signals SEL1 and SEL2 cooperate with each other to select the present track's ATF signal frequency and the succeeding track's ATF signal frequency being the ATF signal frequency of that track shifted in head-scanning relation along the tape by .pi. in terms of the phase of the capstan rotation from the present track as the successive ATF signal frequencies, every one-half period of the head switching signal HSW.
The first and second ATF check comparators 3-5 and 3-6 act to compare the count value from the up-counter 3-2 with the respective ATF check reference values and generate the control signals E1 and E2 as shown in FIG. 4F as a result of the comparison, respectively.
In other words, when a certain track is scanned by the video head, the A/D conversion for the ATF signal is performed two times during each interval between adjacent edges of the head switching signal HSW, i.e., a high level interval or a low level interval of the head switching signal HSW. Points of A/D conversion time are times T1 and T2 lapsed by predetermined time periods from the edge of the head switching signal HSW. For this reason, the first ATF check comparator 3-5 determines the count value from the up-counter 3-2 at the time T1 as the first reference value, compares the output data from the up-counter 3-2 with the first reference value and generates the control signal E1 as a trigger pulse signal if they are the same. Also, the second ATF check comparator 3-6 determines the count value from the up-counter 3-2 at the time T2 as the second reference value, compares the output data from the up-counter 3-2 with the second reference value and generates the control signal E2 as a trigger pulse signal if they are the same.
The control signals E1 and E2 generated in this manner are ORed by the OR gate 3-7 which applies the ORed signal as an enable signal to the A/D converter 3-8. In response to the enable signal, the A/D converter 3-8 converts the analog ATF signal into a digital ATF signal. The subtracter 3-9 subtracts the reference data Dref from the digital ATF signal from the A/D converter 3-8 and loads the difference data into the first and second latches 3-12 and 3-13.
It is herein noted that an ATF error value can be obtained by subtracting Vcc/2 from the ATF signal since the ATF signal is outputted through the amplifier having the reference value of Vcc/2 in the ATF signal detecting circuit 10. As a result, in the subtracter 3-9, the ATF error value is obtained by subtracting the reference data Dref of Vcc/2 from the digital ATF data D.ATF from the A/D converter 3-8.
On the other hand, the control signals E1 and E2 from the first and second ATF check comparators 3-5 and 3-6 are delayed respectively in the first and second delays 3-10 and 3-11 which apply the delayed signals, respectively, as enable signals to the first and second latches 3-12 and 3-13 for latching the output data from the subtracter 3-9. In result, the latches 3-12 and 3-13 latch, respectively, the digital data into which the ATF signals of the present track's ATF signal frequency and the succeeding track's ATF signal frequency (where the ATF signal frequency of the succceeding track is shifted in head-scanning relation along the tape by .pi. in terms of the phase of the capstan rotation from the present track) are converted every one-half period of the head switching signal HSW.
The ATF data A/D-converted at the time of the control signal E1 is the ATF signal of the present track's ATF signal frequency which indicates whether the video head centered on the track having a pilot signal of the frequency f2 leans toward either of the adjacent tracks having respective pilot signals of the frequencies f1 or f3. Also, the ATF data A/D-converted at the time of the control signal E2 is the ATF signal of the succeeding track shifted in head-scanning relation along the tape by .pi. from the present track which indicates whether the video head is centered on the track having a pilot signal of the frequency 12 or f4 among the tracks having respective pilot signals of the frequencies f1-f4. Namely, the data D.ATF1 latched in the first latch 3-12 is normal phase error data and the data D.ATF2 latched in the second latch 3-13 is data for determining the position of the video head.
FIG. 4G shows a voltage waveform of the ATF signal and the points of A/D conversion time for the ATF signal in the case of checking the frequency f2 as the ATF signal frequency. For example, if the video head is centered on the center of the track recorded with the pilot signal of frequency f2, the ATF voltage of the frequency f2 is normally Vcc/2 and the ATF voltage of the frequency f3 is normally higher than Vcc/2. As a result, the ATF error is generated corresponding to a difference when the ATF voltage of the frequency f2 is higher or lower than Vcc/2. If the ATF signal (A/D-converted at the time of the control signal E2) is higher than Vcc/2, the video head is scanning in the middle of the tracks of the frequencies f1, f2 and f3. If the ATF signal (A/D-converted at the time of the control signal E2) is lower than Vcc/2, the video head is scanning in the middle of the tracks of the frequencies f3, f4 and f1.
Accordingly, the ATF voltages of the present track's pilot signal frequency f2 and the succeeding track's pilot signal frequency f3 (where the pilot signal of the succeeding track is shifted in head-scanning relation along the tape by .pi. from the present track and recorded with the pilot signal of frequency f2) are checked to determine whether the track being scanned by the video head is in a normal position and is any one of the tracks respectively recorded with pilot signals of the frequencies f1-f4. The control signals E1 and E2 are generated respectively at times T1 and T2 lapsed by the predetermined time periods from the edges of the head switching signal HSW. The ATF signal of the frequency f2 and the ATF signal of the frequency f3 are A/D-converted respectively based on the generated control signals E1 and E2. In result, the digitized data of the ATF signals after having subtracted therefrom the reference data of Vcc/2 are latched in the first and second latches 3-12 and 3-13, respectively.
The data D.ATF1 latched in the first latch 3-12 is applied to the non-inverting input terminal of the first comparator 3-14 for comparison with the reference value (ground voltage) and the data D.ATF2 latched in the second latch 3-13 is applied to the inverting input terminal of the second comparator 3-15 for comparison with the reference value (ground voltage).
The output signal C.sub.1 from the first comparator 3-14 is applied as a control signal to the first switch 3-16 such that the first switch 3-16 selects the upper limit value U.sub.H from the upper limit circuit 3-18 or the lower limit value U.sub.L from the lower limit circuit 3-19. Also, the output signal C.sub.2 from the second comparator 3-15 is applied as a control signal to the second switch 3-17 such that the second switch 3-17 selects the latch data D.ATF1 from the first latch 3-12 or the output signal from the first switch 3-16 and outputs the selected signal as the phase error signal PE.
If the latch data D.ATF2 from the second latch 3-13 is higher than the reference value (ground voltage), the second switch 3-17 selects the latch data D.ATF1 from the first latch 3-12 and outputs it as the phase error signal PE. On the other hand, if the latch data D.ATF2 from the second latch 3-13 is lower than the reference value (ground potential), the second switch 3-17 selects the output signal from the first switch 3-16. In this case, if the latch data D.ATF1 from the first latch 3-12 is higher than the reference value (ground voltage), the first switch 3-16 selects the upper limit value U.sub.H from the upper limit circuit 3-18. As a result, the second switch 3-16 outputs the upper limit value U.sub.H from the upper limit circuit 3-18 as the phase error signal PE. On the contrary, if the latch data D.ATF1 from the first latch 3-12 is lower than the reference value (ground voltage), the first switch 3-16 selects the lower limit value U.sub.L from the lower limit circuit 3-19. As a result, the second switch 3-16 outputs the lower limit value U.sub.L from the lower limit circuit 3-19 as the phase error signal PE.
Referring to FIGS. 5A to 5C, there are shown timing diagrams for generation of the phase error signal PE in the ATF error detecting circuit 3. The first and second comparators 3-14 and 3-15 control the first and second switches 3-16 and 3-17 at the timing of FIGS. 5A and 5B such that the upper limit value U.sub.H is selected as the phase error signal PE in the interval of -2.pi. to -.pi. of the phase of the capstan as shown in FIG. 5C and the lower limit value U.sub.L is selected as the phase error signal PE in the interval .pi. to 2.pi. of the phase of the capstan as shown in FIG. 5C.
However, the conventional ATF error detecting circuit 3 has a disadvantage, in that a phase control range for the capstan is limited to the interval of -.pi. to .pi. since the upper limit value U.sub.H is outputted as the phase error signal PE regardless of a phase variation in the interval of -2.pi. to -.pi. of the phase of the capstan and the lower limit value U.sub.L is outputted as the phase error signal PE regardless of a phase variation in the interval of .pi. to 2.pi. of the phase of the capstan. Generally in the control of the rotation of the capstan, it is preferred to control the phase variation over the whole of the intervals of -2.pi. to -.pi. and .pi. to 2.pi., of the phase of the capstan. For this reason, in the conventional ATF error detecting circuit 3, since the phase control range for the capstan is limited to the interval of -.pi. to .pi., although the video head tracking of the tape in terms of the phase of the capstan may be deviated by -2.pi. or 2.pi., the convergence speed for stabilization of the phase of the capstan motor is very slow in a range below -.pi. or above .pi.. This results in inappropriateness of the circuit to a high speed system.